By Chuan Seng Tan (auth.), Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantsch (eds.)
Back disguise reproduction sequence: built-in Circuits and structures 3D-Integration for NoC-based SoC Architectures via: (Editors) Abbas Sheibanyrad Frédéric Petrot Axel Janstch This ebook investigates at the delivers, demanding situations, and suggestions for the 3D Integration (vertically stacking) of embedded platforms hooked up through a community on a chip. It covers the full architectural layout strategy for 3D-SoCs. 3D-Integration applied sciences, 3D-Design suggestions, and 3D-Architectures have emerged as subject matters serious for present R&D resulting in a huge variety of goods. This e-book provides a complete, system-level review of 3-dimensional architectures and micro-architectures. •Presents a accomplished, system-level evaluation of third-dimensional architectures and micro-architectures; •Covers the total architectural layout strategy for 3D-SoCs; •Includes cutting-edge remedy of 3D-Integration applied sciences, 3D-Design ideas, and 3D-Architectures.
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Extra info for 3D Integration for NoC-based SoC Architectures
449, 2009. 14. S. Kawamura, N. Sasaki, T. Iwai, M. Nakano, and M. Takagi, Three-Dimensional CMOS ICs Fabricated by Using Beal Recrystallization. Â€366, 1983. 15. T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, Three Dimensional ICs, Having Four Stacked Active Device Layers. Â€837, 1989. 16. V. Subramanian, M. R. J. C. Saraswat, Low-Leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFTs for Vertical Integration Applications. Â€341, 1999. 17. C. H. Chan, and M. Chan, Three-Dimensional CMOS SOI Integrated Circuit Using High-Temperature Metal-Induced Lateral Crystallization.
The reason 35 times more operators fit into the same area is mainly due to the much higher density of DRAM as opposed to SRAM that is common in 2-D based systems. 7c illustrates. It also results in a prohibitively high power consumption since the computation consumes much more power than the memory. Apparently, we cannot power all these computations in reality, but we can translate the increased potential that 3-D offers into either smaller chips, or lower frequency, or higher memory content. 8 shows performance and power consumption for a smaller system (100Â€mm2) clocked at a somewhat lower frequency and at the 35Â€nm technology node.
Ramacher, 3D Chip Stack Technology using Through-Chip Interconnects. IEEE Design & Test of Computers, 22(6), pp. 512–518, 2005. 38. P. Gueguen, L. Di Cioccio, M. Rivoire, D. Scevola, M. M. Charvet, L. Bally, and L. Clavelier, Copper direct bonding for 3D integration. IEEE International Interconnect Technology Conference, pp. 61–63, 2008. 39. T. Osborn, A. He, H. Lightsey, and P. Kohl, All-copper chip-to-substrate interconnects. Proceedings of IEEE Electronic Components and Technology Conference, pp.