Advances in Computer Systems Architecture: 11th Asia-Pacific by Guang R. Gao (auth.), Chris Jesshope, Colin Egan (eds.)

By Guang R. Gao (auth.), Chris Jesshope, Colin Egan (eds.)

On behalf of the entire humans serious about this system choice, this system committee participants in addition to a number of different reviewers, we're either relieved and happy to provide you with the court cases of the 2006 Asia-Pacific computers structure convention (ACSAC 2006), that's being hosted in Shanghai on September 6–8, 2006. this can be the eleventh in a chain of meetings, which all started existence in Australia, because the computing device structure part of the Australian desktop technological know-how Week. In 1999 it ventured clear of its roots for the 1st time, and the fourth Australasian desktop structure convention was once held within the appealing urban of Sails (Auckland, New Zealand). probably it was once due to a scarcity of the other desktop structure convention in Asia or simply the allure of touring to the Southern Hemisphere however the convention grew to become more and more overseas throughout the next 3 years and likewise replaced its identify to incorporate desktops structure, reflecting extra the scope of the convention, which embraces either architectural and structures matters. In 2003, the convention back ventured offshore to mirror its constituency and because then has been held in Japan within the appealing urban of Aizu-Wakamatsu, by means of Beijing and Singapore. This 12 months it back returns to China and subsequent yr will flow to Korea for the 1st time, the place it will likely be prepared by means of the Korea University.

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Additional info for Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings

Example text

In case of branch target misprediction, the penalty is inevitable. However, there is only one case that we can not hide the penalty in case of branch direction misprediction. Since the stored cache line address woken up is not that of (mispredicted branch instruction address + 4), but the mispredicted branch instruction address itself, there is a penalty when the resolved branch instruction is at the end of the cache line and the correct next instruction is sequential. It is possible to make use of the instruction address +4, but it requires extra adder or storage for the instruction address + 4.

On Low Power Electronics and Design, 2000, pp 90-95. 17. G. Reinman and B. Calder. Using a Serial Cache for Energy Efficient Instruction Fetching. Journal of Systems Architecture. vol. 675-685. 18. S. Yang and B. Falsafi. Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches. Proc. of Int. Symp. on Microarchitecture, 2003. 19. S. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar. An Integrated Circuit/ Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance ICaches.

Since the BTB has 1024 entries, the total storage overhead is 10K. For the proposed policy, only a small register (ex. 10 bit for our 1024-entry cache) is needed to record the most recently accessed cache line. 6 Conclusions In this paper, we propose an on-demand wakeup prediction policy using the branch prediction information. Our goal is not only less energy consumption but also consistent near-optimal performance. ) show competitive performance consistently but their energy consumption is more than four times of the proposed policy, on average.

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