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Extra resources for ESD in Silicon Integrated Circuits
Equivalent to the rotation method, the IOpin test cannot be carried out arbitrarily between different groups on different boards. Brodbeck concludes that the split-IO method possibly combined with ganged supplies is most applicable, conceding that there is always a risk that the weak path may be in a combination of IO pins not on the same test fixture board [Brodbeck01]. In this combination, the stress may result in internal current paths that could be missed. Other methods under discussion are to select worst-case combinations covering all types of IO-cells and protection circuits, and supply networks as well as stress conditions from the a priori knowledge of the design.
5 µH. 5 resistor implies a current source characteristic for the low impedances of a fully conducting protection element, a complex interaction between tester and IC may take place during the turn-on phase of the protection element. 4 to protect an IC-input. In this case, a circuit model for the tester was combined with a circuit model for an active protection transistor. 4 Schematics of an IC under HBM-stress in an HBM-tester in detail in Chapters 4 and 11. The complexity of the interaction motivates the preference of simulation over analytical solutions.
8th EOS/ESD Symposium, ESD Association, Rome, NY, USA, pp. 224–231, 1986. 0-1994: Glossary of Terms, 1994. 4: Standard Practice for LatchUp Stressing CMOS/BiCMOS ICs Using Transient Stimulation, Work in Progress 2001. 2-1995: Triboelectric Charge Accumulation Testing, 1995. [Gieser99] H. Gieser, “Verfahren zur Charakterisierung von integrierten Schaltungen mit sehr schnellen Hochstromimpulsen (Methods for the characterisation of integrated circuits employing very fast high current impulses)” in Dissertation Technische Universitaet Muenchen TUM , Shaker-Verlag, Aachen, Germany, 1999.