Graph-Theoretic Concepts in Computer Science: 21st by Evangelos Kranakis, Danny Krizanc (auth.), Manfred Nagl

By Evangelos Kranakis, Danny Krizanc (auth.), Manfred Nagl (eds.)

This e-book constitutes the refereed court cases of the twenty first overseas Workshop on Graph-Theoretic ideas in desktop technology, WG '95, held in Aachen, Germany, in June 1995. The WG workshop sequence contributes to integration in desktop technological know-how via employing graph theoretical strategies in a number of components in addition to by means of taking on difficulties from sensible purposes and treating them theoretically.
The e-book provides 30 rigorously refereed revised papers chosen from fifty two submissions and displays present actions within the box of laptop technology orientated graph concept, its computational features and its application.

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Extra resources for Graph-Theoretic Concepts in Computer Science: 21st International Workshop, WG '95 Aachen, Germany, June 20–22, 1995 Proceedings

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However, the use of large tables is disadvantageous for embedded systems since they occupy scarce memory resources, increase cache pollution, and may open up potential vulnerabilities to cache-based side channel attacks [14]. The MixColumns transformation of AES can be defined as multiplication in an extension field of degree 4 over F28 [3]. Elements of this field are polynomials of degree ≤ 3 with coefficients in F28 . The coefficient field F28 is generated by the irreducible polynomial f (x) = x8 + x4 + x3 + x + 1 (0x11B in hexadecimal notation).

Addition, accumulation, cubing, and multiplication over F397 the dual-port RAM, manage all additions and cubings involved in the computation of the final exponentiation. 4 Results and Comparisons Our final exponentiation coprocessor was implemented on an Altera Cyclone II EP2C35F672C6 FPGA. According to place-and-route tools, this architecture requires 2787 LEs and 21 M4K memory blocks. Since the maximum frequency is 159 MHz, an exponentiation is computed within 26 μs and our timing constraint is fully met.

3 Hardware Implementation This section describes the implementation of Algorithm 6 on a Cyclone II EP2C35F672C6 FPGA whose smallest unit of configurable logic is called Logic Element (LE). Each LE includes a 4-input Look-Up Table (LUT), carry logic, and a programmable register. A Cyclone II EP2C35F672C6 device contains for instance 33216 LEs. Readers who are not familiar with Cyclone II devices should refer to [1] for further details. After studying addition, multiplication, and cubing over F3m , we propose a novel arithmetic operator able to perform these three operations and describe the architecture of a final exponentiation coprocessor based on such a processing element.

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